This specification relates to circuit synthesis with multicycle rules.
An approach to circuit synthesis makes use of an asynchronous system specification to produce a detailed hardware description for a synchronous system, in particular, a clocked (synchronous) digital circuit that functions according to the asynchronous system specification. That is, any sequence of states traversed at clock times of the clocked digital circuit is guaranteed to be a complete (or sampled) sequence of states that may be traversed by the asynchronous system. A compiler can be used to accept the asynchronous system specification and automatically produce a corresponding synchronous circuit specification, for example, specified using the Verilog hardware description language (HDL). One such compiler that performs this task makes use of a Term Rewriting System (TRS) to specify the asynchronous system.
The TRS specification accepted by the compiler includes a set of rules, which are also referred to as guarded atomic actions. Each rule consists of a body and a guard. The body describes the execution behavior of the rule if it is enabled. That is, the body characterizes the change in the state of the system on application of the rule, where the state is defined by the values of storage elements of the system, such as registers or FIFOs. The guard (or predicate) of a rule specifies the condition that needs to be satisfied for the rule to be executable. A rule Ri is written asrule Ri: when πi(s)s:=δi(s)where πi(s) represents the guard and s:=δi(s) represents the body of rule Ri.
One synthesis (i.e., compilation) approach generates combinational logic for each rule's predicate (π) and each rule's state update function (δ). For each clock cycle of the synchronous system, a scheduler chooses one of the rules whose predicate is true (i.e., a rule that is “executable” or “enabled”) and updates the state with the result of the corresponding update function (δ). This process repeats in every clock cycle. Other synthesis approaches each makes use of a scheduler that can enable multiple rules in a single clock cycle, with the multiple rules being selected by the scheduler in such a way that the result is equivalent to a valid sequential application of a set of rules.